LegUp Computing (now part of Microchip Technology) @LegUpComputing
We provide an HLS integrated development environment tool that enables engineers to compile C/C++ software into Verilog targeting Microchip FPGA devices legupcomputing.com Toronto, Ontario Joined February 2018-
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Use our new design methodology, LegUp High-Level Software (HLS) and C++, to achieve better design productivity. Learn more mchp.us/37oIIWW and download the Early Access Program mchp.us/3qw9HY9. #polarfire #fpga #software
Thanks for all the support from the University of Toronto and @UTESTto! The LegUp team is really proud we were able to successfully commercialize our #UofTEngineering research. We're looking forward to the next step of growing our Toronto engineering team with @MicrochipTech
LegUp Computing, a @UofTEngineering startup, acquired by U.S.-based Microchip Technology #UofT 💻 uoft.me/6cG
We are excited to announce that LegUp Computing has been acquired by Microchip! The LegUp HLS integrated development environment will enable Microchip developers to program PolarFire/PolarFireSoC FPGA devices from C/C++. See press release for more details: microchip.com/en/pressreleas…
LegUp HLS 8.0 has just been released! Support added for Achronix’s Speedster7t FPGAs. All FPGA vendors now supported for floating-point/fixed-point/arbitrary bitwidth. Better DSP tech mapping. Added a new image processing library. See release details: legupcomputing.com/blog/index.php…
Andrew Cannis, founder of @LegUpComputing, was extremely impressed with what he saw at SC18. Here is what he had to say about the caliber of #HPC clients in attendance last year. #HPCisNow
LegUp 7.2 has just been released! We now support Xilinx XSIM for simulation/co-simulation. We also now support Xilinx LogiCORE Floating-Point Operator IP Cores. We are also still at #56DAC tomorrow! Come by booth #1127. See release details here: legupcomputing.com/blog/index.php…
LegUp will be exhibiting at the Design Automation Conference #56DAC in Las Vegas, Nevada from June 3-5. Come visit us at booth number 1127 to hear about our next generation high-level synthesis for FPGAs! For updates see: legupcomputing.com/blog/index.php…
Come visit us at the MaRS building for University of Toronto Entrepreneurship Week! We are at booth 55. @UofTStartup
Great to go back at the University of Waterloo to talk about LegUp! We were amazed at how knowledgeable the students were. Thanks Nachiket!
LegUp Computing, a @UofTEngineering startup, acquired by U.S.-based Microchip Technology #UofT 💻 uoft.me/6cG
LegUp 6.7 has been released! We now support automatic loop nest merging to enhance throughput, the multiply-accumulate mode of Intel's hard FP core, up to 14x faster HW/SW Co-simulation of AXI4 slave interface and much more. See more details here: legupcomputing.com/blog/index.php…
LegUp 6.6 has been released! This new version supports generic floating point cores for any FPGA vendor, IP-XACT IP core packaging, CentOS support, and VHDL top-level generation. We also have a new FP multiplier example on github. See more details here: legupcomputing.com/blog/index.php…
We're pleased to announce LegUp 6.5 has been released! This new version supports arbitrary bitwidth integers using the ap_uint C++ class. This allows operations on integers larger than 64 bits. See more details here: legupcomputing.com/blog/index.php…
Andrew Canis and Ruolong Lian are giving a talk today about how @LegUpComputing is accelerating memcached in the datacenter with FPGAs at #XDF2018 in Frankfurt at 5:30pm. Come check us out!
We're pleased to announce a new release: LegUp 6.4! We have support for new features like: Fused multiply-add (FMA) support using hard floating-point DSPs on Intel Arria 10, more control over FIFO implementation, and various bug fixes. See details here: legupcomputing.com/blog/index.php…
Andrew Putnam (@_putnami_) recently gave a great talk about #FPGA at UofToronto: Reconfigurable Computing at HyperScale Video: youtube.com/watch?v=mPi2LH… Slides: drive.google.com/file/d/1W060su…
Come visit us this week at Super Computing 2018! We are showing off FPGA acceleration powered by @LegUpComputing in the startup pavilion at booth 3773 #SC18
We're pleased to announce a new release: LegUp 6.2! We have support for new features like: Intel Arria 10 hard floating point, SW/HW co-simulation of floating point, AXI slave interface (beta), and adding user-defined Verilog modules. See details here: legupcomputing.com/blog/index.php…
Why use an FPGA instead of a CPU or GPU? blog.esciencecenter.nl/why-use-an-fpg… < we need to start getting comfortable with different types of compute accelerators. for a practical example see @LegUpComputing legupcomputing.com/blog/index.php… 🤔
We're pleased to announce a new release: LegUp 6.1! We have many new features like: SW/HW Co-simulation, C++ FIFOs with templates, new FPGA device support for Intel Arria 10, Microsemi PolarFire, and Xilinx Virtex UltraScale+. See more details here: legupcomputing.com/blog/index.php…
Another article about using LeFlow + LegUp for specifying deep neural networks on FPGAs using TensorFlow: nextplatform.com/2018/07/24/cle…
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