Zip CPU @zipcpu
FPGA design engineer and blogger, placing particular emphasis on test and formal verification zipcpu.com Gisselquist Technology, LLC, Joined January 2017-
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"Oh, hey, I can just implement this with a simple delay. No need to verify anything ..." Famous last words followed by 2days -> 1 week of debugging when things don't work.
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eMMC hardware testing this week has gone well. HS200 and HS400 "just worked" (once I got the software right). There's just one significant capability left to test: eMMC BOOT.
With the exception of the formal verification step, these are likely industry standard answers. They don't fit well into classroom lessons, so students tend to learn these in classroom labs rather than lectures.
In general, my techniques include: 1) formal verification, using both assertion based and coverage checks, 2) simulation, 3) self-checking test benches, 4) simulation test suites and regrssions, 5) hardware testing and internal logic analyzers
The entire topic of my blog is about how to find bugs. In an industry where bugs are hidden multi-million dollar mistakes, I like to imagine myself as one of the few voices talking about finding bugs. Here are some articles about finding bugs 🧵
@zipcpu How do you find these bugs? Are you running simulations or whatever with tests or did you just notice it
This bug was found by examining the trace of a failing simulation for basic functionality, and just happening to stumble upon it while reviewing how things were "supposed" to work. Sadly, this wasn't the ultimate bug, but just an unnoticed one. The last bug was found when the simulation hung, so I had to turn tracing on and go dig for it. Today's eMMC bug (not published) was a bit harder to find.
It's a little early in the week for a second bug of the week, but ... this bug passed the inspection of two separate engineers before I finally caught it today. (Yes, I was one of those "two" engineers ...)
How does your product compare against your competitor's product? Think about it. Go big, or go home!
@cortexauth Since this was a simulation only bug , in many ways it is more like software than hardware.
Here's an AXI bug of the week. This routine was required by a test case a helper gave me to get better AxPROT coverage. I thought I'd rewrite it to make it better, then couldn't understand why his test case wasn't finishing ...
Usually someone posts the bug by now. In case everyone missed it, here's what it was: I had confused ARPROT w/ AWPROT.
My office is next to the sewing room where my daughter (who was out) spends her time, and where she also encourages Enzo to join her.
Our dog, Enzo, decided to start sewing this afternoon. He was using the sewing pedal for his pillow.
My first thoughts are to use a simulation helper ...
Today's deeper thought: how do you truly verify AXI exclusive access?
Turns out, it had passed a minimal cover check -- I had just forgotten that when posting. 🙄
Increasing the AXI bus size isn't nearly as difficult as I feared. Now all I need a project to test this on ... You can see my first attempts here: github.com/ZipCPU/wb2axip…
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